ADXL345 3-axis accelerometer

The ADXL345 is a small, thin, ultralow power, 3-axis accelerometer with high resolution (13-bit) measurement at up to ±16 g. Digital output data is formatted as 16-bit twos complement and is accessible through either a SPI (3- or 4-wire) or I2C digital interface.

The ADXL345 is well suited for mobile device applications. It measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion or shock. Its high resolution (3.9 mg/LSB) enables measurement of inclination changes less than 1.0°.

Several special sensing functions are provided. Activity and inactivity sensing detect the presence or lack of motion by comparing the acceleration on any axis with user-set thresholds. Tap sensing detects single and double taps in any direction. Free-fall sensing detects if the device is falling. These functions can be mapped individually to either of two interrupt output pins. An integrated, patent pending memory management system with a 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption.

Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation.

The ADXL345 is supplied in a small, thin, 3 mm × 5 mm × 1 mm, 14-lead, plastic package.

(Source: Analog Devices ADXL345 product description, 3/28/2012)

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Register Map

 R/WBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
[0x00] DEVID

Device ID (DEVID @ 0x00)

Register Bitfields

  • [7:0] DEVID

The DEVID register holds a fixed device ID code of 0xE5 (345 octal).

RO[7:0] DEVID

DEVID @ 0x00

Device ID (DEVID [7:0])

Options

  • 229 = Device ID

The DEVID register holds a fixed device ID code of 0xE5 (345 octal).

[0x1D] THRESH_TAP

Tap threshold (THRESH_TAP @ 0x1D)

Register Bitfields

  • [7:0] THRESH_TAP

The THRESH_TAP register is eight bits and holds the threshold value for tap interrupts. The data format is unsigned, therefore, the magnitude of the tap event is compared with the value in THRESH_TAP for normal tap detection. The scale factor is 62.5 mg/LSB (that is, 0xFF = 16 g). A value of 0 may result in undesirable behavior if single tap/double tap interrupts are enabled.

R/W[7:0] THRESH_TAP

THRESH_TAP @ 0x1D

Tap threshold (THRESH_TAP [7:0])

The THRESH_TAP register is eight bits and holds the threshold value for tap interrupts. The data format is unsigned, therefore, the magnitude of the tap event is compared with the value in THRESH_TAP for normal tap detection. The scale factor is 62.5 mg/LSB (that is, 0xFF = 16 g). A value of 0 may result in undesirable behavior if single tap/double tap interrupts are enabled.

[0x1E] OFSX

X-axis offset (OFSX @ 0x1E)

Register Bitfields

  • [7:0] OFSX

The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 15.6 mg/LSB (that is, 0×7F = 2 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. For additional information regarding offset calibration and the use of the offset registers, refer to the Offset Calibration section.

R/W[7:0] OFSX

OFSX @ 0x1E

X-axis offset (OFSX [7:0])

The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 15.6 mg/LSB (that is, 0×7F = 2 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. For additional information regarding offset calibration and the use of the offset registers, refer to the Offset Calibration section.

[0x1F] OFSY

Y-axis offset (OFSY @ 0x1F)

Register Bitfields

  • [7:0] OFSY

The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 15.6 mg/LSB (that is, 0×7F = 2 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. For additional information regarding offset calibration and the use of the offset registers, refer to the Offset Calibration section.

R/W[7:0] OFSY

OFSY @ 0x1F

Y-axis offset (OFSY [7:0])

The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 15.6 mg/LSB (that is, 0×7F = 2 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. For additional information regarding offset calibration and the use of the offset registers, refer to the Offset Calibration section.

[0x20] OFSZ

Z-axis offset (OFSZ @ 0x20)

Register Bitfields

  • [7:0] OFSZ

The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 15.6 mg/LSB (that is, 0×7F = 2 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. For additional information regarding offset calibration and the use of the offset registers, refer to the Offset Calibration section.

R/W[7:0] OFSZ

OFSZ @ 0x20

Z-axis offset (OFSZ [7:0])

The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 15.6 mg/LSB (that is, 0×7F = 2 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. For additional information regarding offset calibration and the use of the offset registers, refer to the Offset Calibration section.

[0x21] DUR

Tap duration (DUR @ 0x21)

Register Bitfields

  • [7:0] DUR

The DUR register is eight bits and contains an unsigned time value representing the maximum time that an event must be above the THRESH_TAP threshold to qualify as a tap event. The scale factor is 625 μs/LSB. A value of 0 disables the single tap/ double tap functions.

R/W[7:0] DUR

DUR @ 0x21

Tap duration (DUR [7:0])

The DUR register is eight bits and contains an unsigned time value representing the maximum time that an event must be above the THRESH_TAP threshold to qualify as a tap event. The scale factor is 625 μs/LSB. A value of 0 disables the single tap/ double tap functions.

[0x22] LATENT

Tap latency (LATENT @ 0x22)

Register Bitfields

  • [7:0] LATENT

The latent register is eight bits and contains an unsigned time value representing the wait time from the detection of a tap event to the start of the time window (defined by the window register) during which a possible second tap event can be detected. The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function.

R/W[7:0] LATENT

LATENT @ 0x22

Tap latency (LATENT [7:0])

The latent register is eight bits and contains an unsigned time value representing the wait time from the detection of a tap event to the start of the time window (defined by the window register) during which a possible second tap event can be detected. The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function.

[0x23] WINDOW

Tap window (WINDOW @ 0x23)

Register Bitfields

  • [7:0] WINDOW

The window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time (determined by the latent register) during which a second valid tap can begin. The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function.

R/W[7:0] WINDOW

WINDOW @ 0x23

Tap window (WINDOW [7:0])

The window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time (determined by the latent register) during which a second valid tap can begin. The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function.

[0x24] THRESH_ACT

Activity threshold (THRESH_ACT @ 0x24)

Register Bitfields

  • [7:0] THRESH_ACT

The THRESH_ACT register is eight bits and holds the threshold value for detecting activity. The data format is unsigned, so the magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if the activity interrupt is enabled.

R/W[7:0] THRESH_ACT

THRESH_ACT @ 0x24

Activity threshold (THRESH_ACT [7:0])

The THRESH_ACT register is eight bits and holds the threshold value for detecting activity. The data format is unsigned, so the magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if the activity interrupt is enabled.

[0x25] THRESH_INACT

Inactivity threshold (THRESH_INACT @ 0x25)

Register Bitfields

  • [7:0] THRESH_INACT

The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity. The data format is unsigned, so the magnitude of the inactivity event is compared with the value in the THRESH_INACT register. The scale factor is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled.

R/W[7:0] THRESH_INACT

THRESH_INACT @ 0x25

Inactivity threshold (THRESH_INACT [7:0])

The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity. The data format is unsigned, so the magnitude of the inactivity event is compared with the value in the THRESH_INACT register. The scale factor is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled.

[0x26] TIME_INACT

Inactivity time (TIME_INACT @ 0x26)

Register Bitfields

  • [7:0] TIME_INACT

The TIME_INACT register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared. The scale factor is 1 sec/LSB. Unlike the other interrupt functions, which use unfiltered data (see the Threshold section), the inactivity function uses filtered output data. At least one output sample must be generated for the inactivity interrupt to be triggered. This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate. A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register.

R/W[7:0] TIME_INACT

TIME_INACT @ 0x26

Inactivity time (TIME_INACT [7:0])

The TIME_INACT register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared. The scale factor is 1 sec/LSB. Unlike the other interrupt functions, which use unfiltered data (see the Threshold section), the inactivity function uses filtered output data. At least one output sample must be generated for the inactivity interrupt to be triggered. This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate. A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register.

[0x27] ACT_INACT_CTL

Axis enable control for activity and inactivity detection (ACT_INACT_CTL @ 0x27)

Register Bitfields

  • [7] ACT_ACDC
  • [6] ACT_X
  • [5] ACT_Y
  • [4] ACT_Z
  • [3] INACT_ACDC
  • [2] INACT_X
  • [1] INACT_Y
  • [0] INACT_Z

ACT AC/DC and INACT AC/DC Bits

A setting of 0 selects dc-coupled operation, and a setting of 1 enables ac-coupled operation. In dc-coupled operation, the current acceleration magnitude is compared directly with THRESH_ACT and THRESH_INACT to determine whether activity or inactivity is detected.

In ac-coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. New samples of acceleration are then compared to this reference value, and if the magnitude of the difference exceeds the THRESH_ACT value, the device triggers an activity interrupt.

Similarly, in ac-coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. After the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with THRESH_INACT. If the difference is less than the value in THRESH_INACT for the time in TIME_INACT, the device is considered inactive and the inactivity interrupt is triggered.

ACT_x Enable Bits and INACT_x Enable Bits

A setting of 1 enables x-, y-, or z-axis participation in detecting activity or inactivity. A setting of 0 excludes the selected axis from participation. If all axes are excluded, the function is disabled. For activity detection, all participating axes are logically OR’ed, causing the activity function to trigger when any of the participating axes exceeds the threshold. For inactivity detection, all participating axes are logically AND’ed, causing the inactivity function to trigger only if all participating axes are below the threshold for the specified time.

R/W[7] ACT_ACDC

ACT_INACT_CTL @ 0x27

ACT_ACDC [7]

Options

  • 0 = DC-coupled operation
  • 1 = AC-coupled operation

Controls AC/DC-coupled operation of activity detection.

[6] ACT_X

ACT_INACT_CTL @ 0x27

ACT_X [6]

Controls X-axis participation in activity detection.

[5] ACT_Y

ACT_INACT_CTL @ 0x27

ACT_Y [5]

Controls Y-axis participation in activity detection.

[4] ACT_Z

ACT_INACT_CTL @ 0x27

ACT_Z [4]

Controls Z-axis participation in activity detection.

[3] INACT_ACDC

ACT_INACT_CTL @ 0x27

INACT_ACDC [3]

Options

  • 0 = DC-coupled operation
  • 1 = AC-coupled operation

Controls AC/DC-coupled operation of inactivity detection.

[2] INACT_X

ACT_INACT_CTL @ 0x27

INACT_X [2]

Controls X-axis participation in inactivity detection.

[1] INACT_Y

ACT_INACT_CTL @ 0x27

INACT_Y [1]

Controls Y-axis participation in inactivity detection.

[0] INACT_Z

ACT_INACT_CTL @ 0x27

INACT_Z [0]

Controls Z-axis participation in inactivity detection.

[0x28] THRESH_FF

Free-fall threshold (THRESH_FF @ 0x28)

Register Bitfields

  • [7:0] THRESH_FF

The THRESH_FF register is eight bits and holds the threshold value, in unsigned format, for free-fall detection. The acceleration on all axes is compared with the value in THRESH_FF to determine if a free-fall event occurred. The scale factor is 62.5 mg/LSB. Note that a value of 0 mg may result in undesirable behavior if the free-fall interrupt is enabled. Values between 300 mg and 600 mg (0×05 to 0×09) are recommended.

R/W[7:0] THRESH_FF

THRESH_FF @ 0x28

Free-fall threshold (THRESH_FF [7:0])

The THRESH_FF register is eight bits and holds the threshold value, in unsigned format, for free-fall detection. The acceleration on all axes is compared with the value in THRESH_FF to determine if a free-fall event occurred. The scale factor is 62.5 mg/LSB. Note that a value of 0 mg may result in undesirable behavior if the free-fall interrupt is enabled. Values between 300 mg and 600 mg (0×05 to 0×09) are recommended.

[0x29] TIME_FF

Free-fall time (TIME_FF @ 0x29)

Register Bitfields

  • [7:0] TIME_FF

The TIME_FF register is eight bits and stores an unsigned time value representing the minimum time that the value of all axes must be less than THRESH_FF to generate a free-fall interrupt. The scale factor is 5 ms/LSB. A value of 0 may result in undesirable behavior if the free-fall interrupt is enabled. Values between 100 ms and 350 ms (0×14 to 0×46) are recommended.

R/W[7:0] TIME_FF

TIME_FF @ 0x29

Free-fall time (TIME_FF [7:0])

The TIME_FF register is eight bits and stores an unsigned time value representing the minimum time that the value of all axes must be less than THRESH_FF to generate a free-fall interrupt. The scale factor is 5 ms/LSB. A value of 0 may result in undesirable behavior if the free-fall interrupt is enabled. Values between 100 ms and 350 ms (0×14 to 0×46) are recommended.

[0x2A] TAP_AXES

Axis control for single tap/double tap (TAP_AXES @ 0x2A)

Register Bitfields

  • [3] SUPPRESS
  • [2] TAP_X
  • [1] TAP_Y
  • [0] TAP_Z

Controls the tap detection participation settings for each axis, and double-tap suppression.

R/W [3] SUPPRESS

TAP_AXES @ 0x2A

SUPPRESS [3]

Setting the suppress bit suppresses double tap detection if acceleration greater than the value in THRESH_TAP is present between taps. See the Tap Detection section for more details.

[2] TAP_X

TAP_AXES @ 0x2A

TAP_X [2]

A setting of 1 in the TAP_X enable bit enables x-, y-, or z-axis participation in tap detection. A setting of 0 excludes the selected axis from participation in tap detection.

[1] TAP_Y

TAP_AXES @ 0x2A

TAP_Y [1]

A setting of 1 in the TAP_Y enable bit enables x-, y-, or z-axis participation in tap detection. A setting of 0 excludes the selected axis from participation in tap detection.

[0] TAP_Z

TAP_AXES @ 0x2A

TAP_Z [0]

A setting of 1 in the TAP_Z enable bit enables x-, y-, or z-axis participation in tap detection. A setting of 0 excludes the selected axis from participation in tap detection.

[0x2B] ACT_TAP_STATUS

Source of single tap/double tap (ACT_TAP_STATUS @ 0x2B)

Register Bitfields

  • [6] ACT_X
  • [5] ACT_Y
  • [4] ACT_Z
  • [3] ASLEEP
  • [2] TAP_X
  • [1] TAP_Y
  • [0] TAP_Z

ACT_x Source and TAP_x Source Bits

These bits indicate the first axis involved in a tap or activity event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement. When new data is available, these bits are not cleared but are overwritten by the new data. The ACT_TAP_STATUS register should be read before clearing the interrupt. Disabling an axis from participation clears the corresponding source bit when the next activity or single tap/double tap event occurs.

Asleep Bit

A setting of 1 in the asleep bit indicates that the part is asleep, and a setting of 0 indicates that the part is not asleep. This bit toggles only if the device is configured for auto sleep. See the AUTO_SLEEP Bit section for more information on autosleep mode.

RO [6] ACT_X

ACT_TAP_STATUS @ 0x2B

ACT_X [6]

This bit indicates the X axis was involved in an activity event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement.

[5] ACT_Y

ACT_TAP_STATUS @ 0x2B

ACT_Y [5]

This bit indicates the Y axis was involved in an activity event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement.

[4] ACT_Z

ACT_TAP_STATUS @ 0x2B

ACT_Z [4]

This bit indicates the Z axis was involved in an activity event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement.

[3] ASLEEP

ACT_TAP_STATUS @ 0x2B

ASLEEP [3]

A setting of 1 in the asleep bit indicates that the part is asleep, and a setting of 0 indicates that the part is not asleep. This bit toggles only if the device is configured for auto sleep.

[2] TAP_X

ACT_TAP_STATUS @ 0x2B

TAP_X [2]

This bit indicates the X axis was involved in a tap event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement.

[1] TAP_Y

ACT_TAP_STATUS @ 0x2B

TAP_Y [1]

This bit indicates the Y axis was involved in a tap event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement.

[0] TAP_Z

ACT_TAP_STATUS @ 0x2B

TAP_Z [0]

This bit indicates the Z axis was involved in a tap event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement.

[0x2C] BW_RATE

Data rate and power mode control (BW_RATE @ 0x2C)

Register Bitfields

  • [4] LOW_POWER
  • [3:0] RATE

LOW_POWER Bit

A setting of 0 in the LOW_POWER bit selects normal operation, and a setting of 1 selects reduced power operation, which has somewhat higher noise (see the Power Modes section for details).

Rate Bits

These bits select the device bandwidth and output data rate (see Table 7 and Table 8 for details). The default value is 0×0A, which translates to a 100 Hz output data rate. An output data rate should be selected that is appropriate for the communication protocol and frequency selected. Selecting too high of an output data rate with a low communication speed results in samples being discarded.

R/W [4] LOW_POWER

BW_RATE @ 0x2C

LOW_POWER [4]

Options

  • 0 = Normal power
  • 1 = Reduced power

A setting of 0 in the LOW_POWER bit selects normal operation, and a setting of 1 selects reduced power operation, which has somewhat higher noise (see the Power Modes section for details).

[3:0] RATE

BW_RATE @ 0x2C

RATE [3:0]

Options

  • 0 = 0.10 Hz
  • 1 = 0.20 Hz
  • 2 = 0.39 Hz
  • 3 = 0.78 Hz
  • 4 = 1.56 Hz
  • 5 = 3.13 Hz
  • 6 = 6.25 Hz
  • 7 = 12.5 Hz (Low power OK)
  • 8 = 25 Hz (Low power OK)
  • 9 = 50 Hz (Low power OK)
  • 10 = 100 Hz (Low power OK)
  • 11 = 200 Hz (Low power OK)
  • 12 = 400 Hz (Low power OK)
  • 13 = 800 Hz
  • 14 = 1600 Hz
  • 15 = 3200 Hz

These bits select the device bandwidth and output data rate (see Table 7 and Table 8 for details). The default value is 0×0A, which translates to a 100 Hz output data rate. An output data rate should be selected that is appropriate for the communication protocol and frequency selected. Selecting too high of an output data rate with a low communication speed results in samples being discarded.

Table 7. Typical Current Consumption vs. Data Rate

(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)

Output Data Rate (Hz) Bandwidth (Hz) Rate Code IDD (μA)
3200 1600 1111 140
1600 800 1110 90
800 400 1101 140
400 200 1100 140
200 100 1011 140
100 50 1010 140
50 25 1001 90
25 12.5 1000 60
12.5 6.25 0111 50
6.25 3.13 0110 45
3.13 1.56 0101 40
1.56 0.78 0100 34
0.78 0.39 0011 23
0.39 0.20 0010 23
0.20 0.10 0001 23
0.10 0.05 0000 23

Table 8. Typical Current Consumption vs. Data Rate, Low Power Mode

(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)

Output Data Rate (Hz) Bandwidth (Hz) Rate Code IDD (μA)
400 200 1100 90
200 100 1011 60
100 50 1010 50
50 25 1001 45
25 12.5 1000 40
12.5 6.25 0111 34

[0x2D] POWER_CTL

Power-saving features control (POWER_CTL @ 0x2D)

Register Bitfields

  • [5] LINK
  • [4] AUTO_SLEEP
  • [3] MEASURE
  • [2] SLEEP
  • [1:0] WAKEUP

Controls power mode and power-saving features of the accelerometer.

R/W [5] LINK

POWER_CTL @ 0x2D

LINK [5]

Options

  • 0 = Concurrent inactivity/activity detection
  • 1 = Serial inactivity/activity detection

A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is detected. After activity is detected, inactivity detection begins, preventing the detection of activity. This bit serially links the activity and inactivity functions. When this bit is set to 0, the inactivity and activity functions are concurrent. Additional information can be found in the Link Mode section.

When clearing the link bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared.

[4] AUTO_SLEEP

POWER_CTL @ 0x2D

AUTO_SLEEP [4]

If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables the auto-sleep functionality. In this mode, the ADXL345 auto-matically switches to sleep mode if the inactivity function is enabled and inactivity is detected (that is, when acceleration is below the THRESH_INACT value for at least the time indicated by TIME_INACT). If activity is also enabled, the ADXL345 automatically wakes up from sleep after detecting activity and returns to operation at the output data rate set in the BW_RATE register. A setting of 0 in the AUTO_SLEEP bit disables automatic switching to sleep mode. See the description of the Sleep Bit in this section for more information on sleep mode.

If the link bit is not set, the AUTO_SLEEP feature is disabled and setting the AUTO_SLEEP bit does not have an impact on device operation. Refer to the Link Bit section or the Link Mode section for more information on utilization of the link feature.

When clearing the AUTO_SLEEP bit, it is recommended that the part be placed into standby mode and then set back to measure-ment mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the AUTO_SLEEP bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared.

[3] MEASURE

POWER_CTL @ 0x2D

MEASURE [3]

A setting of 0 in the measure bit places the part into standby mode, and a setting of 1 places the part into measurement mode. The ADXL345 powers up in standby mode with minimum power consumption.

[2] SLEEP

POWER_CTL @ 0x2D

SLEEP [2]

A setting of 0 in the sleep bit puts the part into the normal mode of operation, and a setting of 1 places the part into sleep mode. Sleep mode suppresses DATA_READY, stops transmission of data to FIFO, and switches the sampling rate to one specified by the wakeup bits. In sleep mode, only the activity function can be used. When the DATA_READY interrupt is suppressed, the output data registers (Register 0×32 to Register 0×37) are still updated at the sampling rate set by the wakeup bits (D1:D0).

When clearing the sleep bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the sleep bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared.

[1:0] WAKEUP

POWER_CTL @ 0x2D

WAKEUP [1:0]

Options

  • 0 = 1 Hz
  • 1 = 2 Hz
  • 2 = 4 Hz
  • 3 = 8 Hz

These bits control the frequency of readings in sleep mode as described in Table 20.

Table 20. Frequency of Readings in Sleep Mode

Setting Frequency (Hz)
00 8
01 4
10 2
11 1
[0x2E] INT_ENABLE

Interrupt enable control (INT_ENABLE @ 0x2E)

Register Bitfields

  • [7] DATA_READY
  • [6] SINGLE_TAP
  • [5] DOUBLE_TAP
  • [4] ACTIVITY
  • [3] INACTIVITY
  • [2] FREE_FALL
  • [1] WATERMARK
  • [0] OVERRUN

Controls which interrupts are enabled.

R/W[7] DATA_READY

INT_ENABLE @ 0x2E

DATA_READY [7]

The DATA_READY bit is set when new data is available and is cleared when no new data is available.

[6] SINGLE_TAP

INT_ENABLE @ 0x2E

SINGLE_TAP [6]

The SINGLE_TAP bit is set when a single acceleration event that is greater than the value in the THRESH_TAP register (Address 0×1D) occurs for less time than is specified in the DUR register (Address 0×21).

[5] DOUBLE_TAP

INT_ENABLE @ 0x2E

DOUBLE_TAP [5]

The DOUBLE_TAP bit is set when two acceleration events that are greater than the value in the THRESH_TAP register (Address 0×1D) occur for less time than is specified in the DUR register (Address 0×21), with the second tap starting after the time specified by the latent register (Address 0×22) but within the time specified in the window register (Address 0×23). See the Tap Detection section for more details.

[4] ACTIVITY

INT_ENABLE @ 0x2E

ACTIVITY [4]

The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0×24) is experienced on any participating axis, set by the ACT_INACT_CTL register (Address 0×27).

[3] INACTIVITY

INT_ENABLE @ 0x2E

INACTIVITY [3]

The inactivity bit is set when acceleration of less than the value stored in the THRESH_INACT register (Address 0×25) is experienced for more time than is specified in the TIME_INACT register (Address 0×26) on all participating axes, as set by the ACT_INACT_CTL register (Address 0×27). The maximum value for TIME_INACT is 255 sec.

[2] FREE_FALL

INT_ENABLE @ 0x2E

FREE_FALL [2]

The FREE_FALL bit is set when acceleration of less than the value stored in the THRESH_FF register (Address 0×28) is experienced for more time than is specified in the TIME_FF register (Address 0×29) on all axes (logical AND). The FREE_FALL interrupt differs from the inactivity interrupt as follows: all axes always participate and are logically AND’ed, the timer period is much smaller (1.28 sec maximum), and the mode of operation is always dc-coupled.

[1] WATERMARK

INT_ENABLE @ 0x2E

WATERMARK [1]

The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits (Register FIFO_CTL, Address 0×38). The watermark bit is cleared automatically when FIFO is read, and the content returns to a value below the value stored in the samples bits.

[0] OVERRUN

INT_ENABLE @ 0x2E

OVERRUN [0]

The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode. In bypass mode, the overrun bit is set when new data replaces unread data in the DATAX, DATAY, and DATAZ registers (Address 0×32 to Address 0×37). In all other modes, the overrun bit is set when FIFO is filled. The overrun bit is automatically cleared when the contents of FIFO are read.

[0x2F] INT_MAP

Interrupt mapping control (INT_MAP @ 0x2F)

Register Bitfields

  • [7] DATA_READY
  • [6] SINGLE_TAP
  • [5] DOUBLE_TAP
  • [4] ACTIVITY
  • [3] INACTIVITY
  • [2] FREE_FALL
  • [1] WATERMARK
  • [0] OVERRUN

Controls interrupt pin mapping for each internal interrupts. Any bits set to 0 in this register send their respective interrupts to the INT1 pin, whereas bits set to 1 send their respective interrupts to the INT2 pin. All selected interrupts for a given pin are OR’ed.

R/W[7] DATA_READY

INT_MAP @ 0x2F

DATA_READY [7]

Options

  • 0 = INT1 pin
  • 1 = INT2 pin

The DATA_READY bit is set when new data is available and is cleared when no new data is available.

[6] SINGLE_TAP

INT_MAP @ 0x2F

SINGLE_TAP [6]

Options

  • 0 = INT1 pin
  • 1 = INT2 pin

The SINGLE_TAP bit is set when a single acceleration event that is greater than the value in the THRESH_TAP register (Address 0×1D) occurs for less time than is specified in the DUR register (Address 0×21).

[5] DOUBLE_TAP

INT_MAP @ 0x2F

DOUBLE_TAP [5]

Options

  • 0 = INT1 pin
  • 1 = INT2 pin

The DOUBLE_TAP bit is set when two acceleration events that are greater than the value in the THRESH_TAP register (Address 0×1D) occur for less time than is specified in the DUR register (Address 0×21), with the second tap starting after the time specified by the latent register (Address 0×22) but within the time specified in the window register (Address 0×23). See the Tap Detection section for more details.

[4] ACTIVITY

INT_MAP @ 0x2F

ACTIVITY [4]

Options

  • 0 = INT1 pin
  • 1 = INT2 pin

The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0×24) is experienced on any participating axis, set by the ACT_INACT_CTL register (Address 0×27).

[3] INACTIVITY

INT_MAP @ 0x2F

INACTIVITY [3]

Options

  • 0 = INT1 pin
  • 1 = INT2 pin

The inactivity bit is set when acceleration of less than the value stored in the THRESH_INACT register (Address 0×25) is experienced for more time than is specified in the TIME_INACT register (Address 0×26) on all participating axes, as set by the ACT_INACT_CTL register (Address 0×27). The maximum value for TIME_INACT is 255 sec.

[2] FREE_FALL

INT_MAP @ 0x2F

FREE_FALL [2]

Options

  • 0 = INT1 pin
  • 1 = INT2 pin

The FREE_FALL bit is set when acceleration of less than the value stored in the THRESH_FF register (Address 0×28) is experienced for more time than is specified in the TIME_FF register (Address 0×29) on all axes (logical AND). The FREE_FALL interrupt differs from the inactivity interrupt as follows: all axes always participate and are logically AND’ed, the timer period is much smaller (1.28 sec maximum), and the mode of operation is always dc-coupled.

[1] WATERMARK

INT_MAP @ 0x2F

WATERMARK [1]

Options

  • 0 = INT1 pin
  • 1 = INT2 pin

The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits (Register FIFO_CTL, Address 0×38). The watermark bit is cleared automatically when FIFO is read, and the content returns to a value below the value stored in the samples bits.

[0] OVERRUN

INT_MAP @ 0x2F

OVERRUN [0]

Options

  • 0 = INT1 pin
  • 1 = INT2 pin

The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode. In bypass mode, the overrun bit is set when new data replaces unread data in the DATAX, DATAY, and DATAZ registers (Address 0×32 to Address 0×37). In all other modes, the overrun bit is set when FIFO is filled. The overrun bit is automatically cleared when the contents of FIFO are read.

[0x30] INT_SOURCE

Source of interrupts (INT_SOURCE @ 0x30)

Register Bitfields

  • [7] DATA_READY
  • [6] SINGLE_TAP
  • [5] DOUBLE_TAP
  • [4] ACTIVITY
  • [3] INACTIVITY
  • [2] FREE_FALL
  • [1] WATERMARK
  • [0] OVERRUN
RO[7] DATA_READY

INT_SOURCE @ 0x30

DATA_READY [7]

The DATA_READY bit is set when new data is available and is cleared when no new data is available.

[6] SINGLE_TAP

INT_SOURCE @ 0x30

SINGLE_TAP [6]

The SINGLE_TAP bit is set when a single acceleration event that is greater than the value in the THRESH_TAP register (Address 0×1D) occurs for less time than is specified in the DUR register (Address 0×21).

[5] DOUBLE_TAP

INT_SOURCE @ 0x30

DOUBLE_TAP [5]

The DOUBLE_TAP bit is set when two acceleration events that are greater than the value in the THRESH_TAP register (Address 0×1D) occur for less time than is specified in the DUR register (Address 0×21), with the second tap starting after the time specified by the latent register (Address 0×22) but within the time specified in the window register (Address 0×23). See the Tap Detection section for more details.

[4] ACTIVITY

INT_SOURCE @ 0x30

ACTIVITY [4]

The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0×24) is experienced on any participating axis, set by the ACT_INACT_CTL register (Address 0×27).

[3] INACTIVITY

INT_SOURCE @ 0x30

INACTIVITY [3]

The inactivity bit is set when acceleration of less than the value stored in the THRESH_INACT register (Address 0×25) is experienced for more time than is specified in the TIME_INACT register (Address 0×26) on all participating axes, as set by the ACT_INACT_CTL register (Address 0×27). The maximum value for TIME_INACT is 255 sec.

[2] FREE_FALL

INT_SOURCE @ 0x30

FREE_FALL [2]

The FREE_FALL bit is set when acceleration of less than the value stored in the THRESH_FF register (Address 0×28) is experienced for more time than is specified in the TIME_FF register (Address 0×29) on all axes (logical AND). The FREE_FALL interrupt differs from the inactivity interrupt as follows: all axes always participate and are logically AND’ed, the timer period is much smaller (1.28 sec maximum), and the mode of operation is always dc-coupled.

[1] WATERMARK

INT_SOURCE @ 0x30

WATERMARK [1]

The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits (Register FIFO_CTL, Address 0×38). The watermark bit is cleared automatically when FIFO is read, and the content returns to a value below the value stored in the samples bits.

[0] OVERRUN

INT_SOURCE @ 0x30

OVERRUN [0]

The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode. In bypass mode, the overrun bit is set when new data replaces unread data in the DATAX, DATAY, and DATAZ registers (Address 0×32 to Address 0×37). In all other modes, the overrun bit is set when FIFO is filled. The overrun bit is automatically cleared when the contents of FIFO are read.

[0x31] DATA_FORMAT

Data format control (DATA_FORMAT @ 0x31)

Register Bitfields

  • [7] SELF_TEST
  • [6] SPI
  • [5] INT_INVERT
  • [3] FULL_RES
  • [2] JUSTIFY
  • [1:0] RANGE

The DATA_FORMAT register controls the presentation of data to Register 0×32 through Register 0×37. All data, except that for the ±16 g range, must be clipped to avoid rollover.

R/W[7] SELF_TEST

DATA_FORMAT @ 0x31

SELF_TEST [7]

A setting of 1 in the SELF_TEST bit applies a self-test force to the sensor, causing a shift in the output data. A value of 0 disables the self-test force.

[6] SPI

DATA_FORMAT @ 0x31

SPI [6]

Options

  • 0 = 3-wire SPI mode
  • 1 = 4-wire SPI mode

A value of 1 in the SPI bit sets the device to 3-wire SPI mode, and a value of 0 sets the device to 4-wire SPI mode.

[5] INT_INVERT

DATA_FORMAT @ 0x31

INT_INVERT [5]

Options

  • 0 = Active high (normal)
  • 1 = Active low (inverted)

A value of 0 in the INT_INVERT bit sets the interrupts to active high, and a value of 1 sets the interrupts to active low.

 [3] FULL_RES

DATA_FORMAT @ 0x31

FULL_RES [3]

When this bit is set to a value of 1, the device is in full resolution mode, where the output resolution increases with the g range set by the range bits to maintain a 4 mg/LSB scale factor. When the FULL_RES bit is set to 0, the device is in 10-bit mode, and the range bits determine the maximum g range and scale factor.

[2] JUSTIFY

DATA_FORMAT @ 0x31

JUSTIFY [2]

Options

  • 0 = Right-justified w/sign extension
  • 1 = Left-justified (MSB) mode

A setting of 1 in the justify bit selects left-justified (MSB) mode, and a setting of 0 selects right-justified mode with sign extension.

[1:0] RANGE

DATA_FORMAT @ 0x31

RANGE [1:0]

Options

  • 0 = ±2 g
  • 1 = ±4 g
  • 2 = ±8 g
  • 3 = ±16 g

These bits set the g range as described in Table 21.

Table 21. g Range Setting

Setting g Range
00 ±2 g
01 ±4 g
10 ±8 g
11 ±16 g
[0x32] DATAX0

X-Axis Data 0 (DATAX0 @ 0x32)

Register Bitfields

  • [15:0] DATAX

X-axis accelerometer measurement data. The output data is twos complement, with DATAx0 as the least significant byte and DATAx1 as the most significant byte, where x represent X, Y, or Z. The DATA_FORMAT register (Address 0×31) controls the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data between reads of sequential registers.

RO[15:0] DATAX

DATAX0 @ 0x32

DATAX [15:0]

X-axis accelerometer measurement.

[0x33] DATAX1

X-Axis Data 1 (DATAX1 @ 0x33)

RO
[0x34] DATAY0

Y-Axis Data 0 (DATAY0 @ 0x34)

Register Bitfields

  • [15:0] DATAY

Y-axis accelerometer measurement data. The output data is twos complement, with DATAx0 as the least significant byte and DATAx1 as the most significant byte, where x represent X, Y, or Z. The DATA_FORMAT register (Address 0×31) controls the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data between reads of sequential registers.

RO[15:0] DATAY

DATAY0 @ 0x34

DATAY [15:0]

Y-axis accelerometer measurement.

[0x35] DATAY1

Y-Axis Data 1 (DATAY1 @ 0x35)

RO
[0x36] DATAZ0

Z-Axis Data 0 (DATAZ0 @ 0x36)

Register Bitfields

  • [15:0] DATAZ

Z-axis accelerometer measurement data. The output data is twos complement, with DATAx0 as the least significant byte and DATAx1 as the most significant byte, where x represent X, Y, or Z. The DATA_FORMAT register (Address 0×31) controls the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data between reads of sequential registers.

RO[15:0] DATAZ

DATAZ0 @ 0x36

DATAZ [15:0]

Z-axis accelerometer measurement.

[0x37] DATAZ1

Z-Axis Data 1 (DATAZ1 @ 0x37)

RO
[0x38] FIFO_CTL

FIFO control (FIFO_CTL @ 0x38)

Register Bitfields

  • [7:6] FIFO_MODE
  • [5] TRIGGER
  • [4:0] SAMPLES

Controls the behavior of the internal FIFO.

R/W[7:6] FIFO_MODE

FIFO_CTL @ 0x38

FIFO_MODE [7:6]

Options

  • 0 = Bypass
  • 1 = FIFO
  • 2 = Stream
  • 3 = Trigger

These bits set the FIFO mode, as described in Table 22.

Table 22. FIFO Modes

Setting Mode Function
00 Bypass FIFO is bypassed.
01 FIFO FIFO collects up to 32 values and then stops collecting data, collecting new data only when FIFO is not full.
10 Stream FIFO holds the last 32 data values. When FIFO is full, the oldest data is overwritten with newer data.
11 Trigger When triggered by the trigger bit, FIFO holds the last data samples before the trigger event and then continues to collect data until full. New data is collected only when FIFO is not full.
[5] TRIGGER

FIFO_CTL @ 0x38

TRIGGER [5]

Options

  • 0 = INT1
  • 1 = INT2

A value of 0 in the trigger bit links the trigger event of trigger mode to INT1, and a value of 1 links the trigger event to INT2.

[4:0] SAMPLES

FIFO_CTL @ 0x38

SAMPLES [4:0]

The function of these bits depends on the FIFO mode selected (see Table 23). Entering a value of 0 in the samples bits immediately sets the watermark status bit in the INT_SOURCE register, regardless of which FIFO mode is selected. Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used.

Table 23. Samples Bits Functions

FIFO Mode Samples Bits Function
Bypass None.
FIFO Specifies how many FIFO entries are needed to trigger a watermark interrupt.
Stream Specifies how many FIFO entries are needed to trigger a watermark interrupt.
Trigger Specifies how many FIFO samples are retained in the FIFO buffer before a trigger event.
[0x39] FIFO_STATUS

FIFO status (FIFO_STATUS @ 0x39)

Register Bitfields

  • [7] FIFO_TRIG
  • [5:0] ENTRIES

Contains information about the current FIFO status and size.

RO[7] FIFO_TRIG

FIFO_STATUS @ 0x39

FIFO_TRIG [7]

A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring, and a 0 means that a FIFO trigger event has not occurred.

 [5:0] ENTRIES

FIFO_STATUS @ 0x39

ENTRIES [5:0]

These bits report how many data values are stored in FIFO. Access to collect the data from FIFO is provided through the DATAX, DATAY, and DATAZ registers. FIFO reads must be done in burst or multiple-byte mode because each FIFO level is cleared after any read (single- or multiple-byte) of FIFO. FIFO stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device.