Simon Posted February 13 Report Share Posted February 13 I note that the offset calibration routine here basically uses a PID loop to determine the best hardware acceleration calibration. New Theory: The reason this works far better that the description in the 'MPU Hardware Offset Registers Application Note' where they just add the discovered offsets to existing values is that the HW offsets are applied before a HW scale is applied. You can calculate the 'scale' applied by changing the hardware offsets by a known value, and read the data output before and after. For me, the scale factors are [1.078, 1.111, 1.171] So, if you then set the hardware offsets to zero, measure the output, and then set the hardware offsets to the measured outputs multiplied by the scale factors, then the subsequent measured values are very close to zero.... I'm guessing that these scale factors different for each device, and are also in the registers somewhere... but have yet to establish where. (the reason I went this route is because I'm running over pigpio, so all i2c coms are over network, hence the PID loop is not so efficient for me...). Thoughts? Quote Link to comment Share on other sites More sharing options...
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